“Aggelos Kavaleros is a Digital Design and Verification Engineer currently pursuing a Ph.D. in Electrical and Computer Engineering at the Democritus University of Thrace, where he also earned his Integrated Master’s degree. His research focuses on specialized integrated circuits using heterogeneous chiplets for accelerating machine learning applications.
At Smart Silicon, Aggelos has contributed to the UVM, formal verification and system-level design of digital components, including CAN protocol verification, APB-to-AHB bridge development, and clock-switching circuits. His work reflects a strong combination of academic insight and hands-on engineering practice.
During his studies, he developed and verified a pipelined processor with hazard detection and forwarding mechanisms, using assembly and Python-based testbenches, demonstrating practical skills in debugging and digital design using SystemVerilog.
Aggelos is proficient in SystemVerilog, VHDL, C/C++, and Python, and has experience with industry-standard tools including Vivado, QuestaSim, Catapult HLS, Jasper Gold, and SpyGlass. Fluent in English (C2 level), he brings a strong foundation in high-level synthesis, UVM, formal verification, and embedded systems design.”
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