“Orestis Andreas Liakopoulos is a Senior Digital Verification Engineer at Smart Silicon, with several years of experience in functional and formal verification of complex digital systems. He specializes in building scalable, reusable UVM-based testbenches and applies modern verification methodologies to deliver high-quality, reliable ASIC and SoC designs.
His technical expertise includes SystemVerilog, UVM, formal verification, SystemVerilog Assertions (SVA), and scripting in Python, C, and MATLAB. He has worked on a variety of verification flows, from IP-level environments to chip-level integration, consistently contributing to projects with a strong focus on coverage, debug efficiency, and regression stability.
Orestis holds a Master’s Degree in Electronic Automation from the National and Kapodistrian University of Athens, with academic foundations in programming, computer science, and digital systems. His educational path combined coursework from the Faculties of Physics and Informatics, giving him a broad and multidisciplinary technical base.
At Smart Silicon, he plays a key role in executing verification plans, mentoring junior engineers, and maintaining verification infrastructure. Known for his structured mindset and deep attention to detail, Orestis brings both rigor and adaptability to safety- and performance-critical design projects.”
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