“Stelios Psillakis serves as a Digital and Mixed-Signal Design Engineer at Smart Silicon, where he focuses on real-number behavioral modeling and cross-verification of analog models against schematics. He also contributes to backend development, including RTL coding, synthesis, place & route, and STA sign-off, having worked across technology nodes from 20nm to 130nm. Prior to joining Smart Silicon, he worked at Weasic Microelectronics AE, where he developed both digital and analog IPs. Stelios is proficient in Cadence Genus, Innovus, and Virtuoso, and also brings experience in FPGA programming and practical analog design.
Stelios has deep expertise in real-number behavioral modeling and cross-verification of behavioral models against schematics, enabling reliable integration and validation of mixed-signal designs. He also brings practical experience in FPGA programming and analog circuit development, making him a versatile contributor across the design stack.
Outside of engineering, Stelios is passionate about electronics, programming, and meaningful community engagement through volunteer work.”
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